1. Field of the Invention
The invention relates to memory circuits, particularly to SRAM circuits.
2. Description of the Related Art
SRAM (static random access memory) is internally organized as illustrated in FIG. 1. The SRAM-type memory comprises a memory cell array 15 of 1-bit memory cells 1 with m rows and n columns. Each memory cell is based on a flip-flop (typically CMOS-type) as the memory core cell with positive feedback for the storage of the data (not shown). The differential data outputs of the flip-flop are selectively coupled to differential bit lines blj and blnj by memory cell internal select transistors (not shown), which are driven by a corresponding word line wli. The bit lines blj and blnj are usually precharged to a specific voltage level (usually the supply voltage Vdd) by precharging circuits P.
Each memory cell 1 is addressed by a row address signal 2 and a column address signal 3 with Id(m)- and Id(n)-bit word-length, respectively. The row address signal 2 is decoded in a row decoder 4 to select one of the m rows. In a similar way, the column address signal 3 is decoded in a column decoder 5 to select one of the n columns. Each row of memory cells is coupled to one word line wli. In the event a row is selected, the corresponding word line wli exhibits a logically high potential. The selection of a word line is resetable by a signal wl_resetn which resets all word lines to a logically low level in case wl_resetn is high. This is realized by m AND-gates driving the m word lines, with each AND-gate being connected to one output signal ai of the row decoder and the signal wl_resetn. For the selection of one of the n columns each of the n output signals of the column decoder 5 is connected to one of n total column switches 6. In the event a column is selected, the corresponding pair of differential bit lines blj and blnj is connected to the differential pair of data I/O lines 7 via the corresponding column switch 6.
For read access and write access the data I/O lines 7 are connected to the differential input sa and san of a sense amplifier 8 and to the differential output of a write buffer 9, respectively. In general, a dynamic sense amplifier 8 is employed, with its operation being controlled by a control signal saen. The signal saen activates the amplifier 8 when switching from low to high. The dynamic sense amplifier 8 is based on an internal positive feedback, which speeds up the signal detection compared to a static sense amplifier. In addition, a dynamic sense amplifier 8 also consumes less power compared to a static sense amplifier since it switches to zero power as soon as it has made a decision. Similar to the dynamic sense amplifier 8, the operation of the write buffer 9 is controlled by a control signal irwb which activates or deactivates the driving of the I/O data lines 7 and the therewith connected bit lines blj and blnj, when switching from low to high level or from high to low level, respectively.
FIG. 2 illustrates the SRAM-internal timing during a memory read access. The transient voltage curves 10 and 11 are related to the differential inputs sa and san of the sense amplifier 8, whereas the transient voltage curve 12 relates to the control signal saen for sense amplifier activation. At the beginning of the memory read process the inputs sa and san and the connected bit lines blj and blnj are still precharged to Vdd, with Vdd being the positive supply voltage. The recharge of the inputs sa and san with respect to the memory cell internal voltages is delayed because of parasitic capacitances (mainly parasitic capacitances of the bit lines blj and blnj). At a time instant ta the sense amplifier 8 is activated when the control signal saen switches from low to high. The differential voltage between the signals sa and san at the time instant ta is defined as the read margin Δsa. The earlier the sense amplifier 8 is activated, the smaller Δsa is and the faster the read operation is. But the smaller Δsa is, the more critical the detection of the signal is that is read out of the memory cell. Since the recharging capability of a selected memory cell 1 may vary from memory circuit to memory circuit as well as from memory cell to memory cell and in addition the detection capability of a sense amplifier 8 may vary from memory circuit to memory circuit, the read margin Δsa is typically set as a value which provides a desired level of safe operation. Thus, there is a trade-off between memory speed and safety of operation when setting the read margin Δsa. At the end of the read operation the wordline wli is deactivated by switching the signal wl_resetn (cf. FIG. 1) from high to low (not shown).
FIG. 3 illustrates the SRAM-internal timing during a memory write access. The transient voltage curves 20 and 21 are related to the signal on the selected word line wli and the signal irwb which controls the operation of the write buffer 9, respectively. The transient voltage curves 22 and 23 relate to differential internal voltage levels c and cn of the flip-flop in the selected memory cell. The transient voltage curves 24 and 25 relate to the voltage levels on the differential bit line blj and blnj. For the write access, first the signal irwb is switched from low to high to activate the write buffer 9. After the signal on the selected word line wli switches from low to high, a recharge of the bit lines blj and blnj and the internal voltages c and cn of the selected flip-flop according to the data input signal of the write buffer 9 is initiated. After the recharge of the internal voltages c and cn is sufficient to switch the state of the flip-flop (due to flip-flop internal positive feedback), the write buffer 9 is deactivated by switching the signal irwb from high to low. The word line wli has to be maintained activated during the commutation of the flip-flop. Afterwards the wordline wli is deactivated by switching the signal wl_resetn (cf. FIG. 1) from high to low (not shown). After closing the wordline (and typically not before) the differential bit line blj and blnj is recharged to a precharging level by the precharging circuits P (cf. FIG. 1). For the write access, the write margin Δt is a defined time-based value. The write margin Δt is defined by the time window which is described by the time instance t1 when the flip-flop-internal node-voltage cn crosses Vdd/2 and the time instance t2 when the falling edge of the voltage on the word line wli crosses Vdd/2 (word line deactivation). The larger the write margin Δt, the later the word line wli is deactivated and the more a correct commutation of the flip-flop is guaranteed. The smaller the write margin Δt is, the faster the write operation is. Thus, there is a trade-off between memory speed and safety of operation when setting the write margin Δt.
The document U.S. Pat. No. 5,936,905 describes a self-adjusting delay circuit in an SRAM circuit. The delay circuit relates only to read access and adjusts the internal timing with respect to the activation of a dynamic sense amplifier. The delay circuit comprises a dummy word line which replicates a corresponding word line and is connected to a number n of parallel dummy transistors. The number n of parallel dummy transistors is the same than the number of transistors connected to the corresponding word line. A subset m of these n dummy transistors drives a dummy bit line which replicates a corresponding bit line. The activation signal related to the dynamic sense amplifier is derived from the voltage level on the dummy bit line. To counteract process variation regarding the characteristics of the memory circuit and therewith related timing mismatch, the delay of the delay circuit is programmable by setting the number of transistors m driving the dummy bit line.
Due to these above-mentioned timing constraints, state-of-the-art memory circuits, particularly SRAM circuits, are only operational within a small range of the nominal supply voltage. In case the actual applied supply voltage is lower, the read margin Δsa and the write margin Δt might be too small and the operation of the memory circuit might fail.
In such SRAM circuits, the supply voltage may be constant. However, in some cases, a constant supply voltage may have undesirable dynamic and static power consumption. Accordingly, what is needed is a method and apparatus for reducing dynamic and static power consumption in a SRAM circuit.